• 128 pin QFP/LQFP (pin-to-pin compatible with the RTL8139C(L))
• Software compatible to the RTL8139 series when configured in RTL8139C mode (C mode) Supports descriptor-based buffer management when configured in RTL8139C+ mode (C+ mode)
• Supports IEEE802.1Q VLAN tagging in C+ mode
• Supports Transmit (Tx) Priority Queue for QoS, CoS applications in C+ mode
• Integrated Fast Ethernet MA C, PHY and transceiver in one chip
• 10Mbps and 100Mbps operation
• Supports 10Mbps and 100Mbps N-way Auto-negotiation operation
• PCI local bus single-chip Fast Ethernet controller
  • Compliant to PCI Revision 2.2
  • Supports PCI clocks 16.75MHz-40MHz
  • Supports PCI target fast back-to-back transaction
  • Supports Memory Read Line, Memory Read Multiple, Memory Write and Invalidate, and Dual Address Cycle, when set to C+ mode.
  • Provides PCI bus master data transfers and PCI memory space or I/O space mapped data transfers of the RTL8139C(L)+’s operational registers
  • Supports PCI VPD (Vital Product Data)
  • Supports ACPI, PCI power management
  • Supports optional PCI multi-function with additional function in slave mode only.
• Supports CardBus. The CIS can be stored in the 93C56 or expansion ROM
• Supports either MII or Boot ROM interface, though only one interface can be implemented at a time. Up to 128K byte Boot ROM interface for both EPROM and Flash memory can be supported

• Supports 25MHz crystal or 25MHz OSC as the internal clock source. The frequency deviation of either crystal or OSC must be within 50 PPM
• Compliant to PC99 and PC2001 standards
• Supports Wake-On-LAN function and remote wake-up (Magic Packet*, LinkChg and Microsoft wake-up frame)
• Supports 4 Wake-On-LAN (WOL) signals (active high, active low, positive pulse, and negative pulse)
• Supports auxiliary power-on internal reset, to be ready for remote wake-up when main power still remains off
• Supports auxiliary power auto-detect, and sets the related capability of power management registers in PCI configuration space
• Includes a programmable, PCI burst size and early Tx/Rx threshold
• Supports a 32-bit general-purpose timer with the external PCI clock as clock source, to generate timer-interrupt
• Contains two large (2Kbyte) independent receive (Rx) and transmit (Tx) FIFOs
• Advanced power saving mode when LAN function or wakeup function is not used
• Uses 93C46 (64*16-bit EEPROM) or 93C56 (128*16-bit EEPROM) to store resource configuration, ID parameter, and VPD data. The 93C56 can also be used to store the CIS data structure for the CardBus application
• Supports LED pins for various network activity indications
• Supports digital and analog loopback capability on both ports
• Half/Full duplex capability
• Supports Full Duplex Flow Control (IEEE 802.3x)
• 3.3V power supply with 5V tolerant I/Os

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